Design and Implementation of a Fault Tolerant Magnetic Bearings Controller

A digital controller designed to meet the demanding performance and reliability requirements of high-speed magnetic bearing applications is presented. The controller architecture is a fault-tolerant design, consisting of four processor modules arranged in a triple modular redundant (TMR) configuration with a hot spare. A voting module provides active repair and reconfiguration in the event of data disagreements or "lost" processors. The processor modules are independent computers based on the Texas Instruments' TMS320C40, a high speed 32-bit floating point digital signal processor (DSP), capable of executing 220 million operations per second (MOPs). Reliability is further enhanced by a fault tolerant IJO bus, whose data / address buses are each augmented with a set of check bits for single-bit error correction (SEC). Support for the development of control algorithms is provided by a multi-tasking, real-time operating system (RTOS).